Title:         Figures

Title: Figures

Fig.1-1     Example Data Structure
Fig.2-1     Two-Component Pointer
Fig.2-2     Fundamental Data Types
Fig.2-3     Bytes, Words, and Doublewords in Memory
Fig.2-4     80386 Data Types
Fig.2-5     80386 Applications Register Set
Fig.2-6     Use of Memory Segmentation
Fig.2-7     80386 Stack
Fig.2-8     EFLAGS Register
Fig.2-9     Instruction Pointer Register
Fig.2-10    Effective Address Computation
Fig.3-1     PUSH
Fig.3-2     PUSHA
Fig.3-3     POP
Fig.3-4     POPA
Fig.3-5     Sign Extension
Fig.3-6     SAL and SHL
Fig.3-7     SHR
Fig.3-8     SAR
Fig.3-9     Using SAR to Simulate IDIV
Fig.3-10    Shift Left Double
Fig.3-11    Shift Right Double
Fig.3-12    ROL
Fig.3-13    ROR
Fig.3-14    RCL
Fig.3-15    RCR
Fig.3-16    Formal Definition of the ENTER Instruction
Fig.3-17    Variable Access in Nested Procedures
Fig.3-18    Stack Frame for MAIN at Level 1
Fig.3-19    Stack Frame for Prooedure A
Fig.3-20    Stack Frame for Procedure B at Level 3 Called from A
Fig.3-21    Stack Frame for Procedure C at Level 3 Called from B
Fig.3-22    LAHF and SAHF
Fig.3-23    Flag Format for PUSHF and POPF
Fig.4-1     Systems Flags of EFLAGS Register
Fig.4-2     Control Registers
Fig.5-1     Address Translation Overview
Fig.5-2     Segment Translation
Fig.5-3     General Segment-Descriptor Format
Fig.5-4     Format of Not-Present Descriptor
Fig.5-5     Descriptor Tables
Fig.5-6     Format of a Selector
Fig.5-7     Segment Registers
Fig.5-8     Format of a Linear Address
Fig.5-9     Page Translation
Fig.5-10    Format of a Page Table Entry
Fig.5-11    Invalid Page Table Entry
Fig.5-12    80386 Addressing Mechanism
Fig.5-13    Descriptor per Page Table
Fig.6-1     Protection Fields of Segment Descriptors
Fig.6-2     Levels of Privilege
Fig.6-3     Privilege Check for Data Access
Fig.6-4     Privilege Check for Control Transfer without Gate
Fig.6-5     Format of 80386 Call Gate
Fig.6-6     Indirect Transfer via Call Gate
Fig.6-7     Privilege Check via Call Gate
Fig.6-8     Initial Stack Pointers of TSS
Fig.6-9     Stack Contents after an Interievel Call
Fig.6-10    Protection Fields of Page Table Entries
Fig.7-1     80386 32-Bit Task State Segment
Fig.7-2     TSS Descriptor for 32-Bit TSS
Fig.7-3     Task Register
Fig.7-4     Task Gate Descriptor
Fig.7-5     Task Gate Indirectly Identifies Task
Fig.7-6     Partially-Overlapping Linear Spaces
Fig.8-1     Memory-Mapped I/O
Fig.8-2     I/O Address Bit Map
Fig.9-1     IDT Register and Table
Fig.9-2     Pseudo-Descriptor Format for LIDT and SIDT
Fig.9-3     80386 IDT Gate Descriptors
Fig.9-4     Interrupt Vectoring for Procedures
Fig.9-5     Stack Layout after Exception of Interrupt
Fig.9-6     Interrupt Vectoring for Tasks
Fig.9-7     Error Code Format
Fig.9-8     Page-Fault Error Code Format
Fig.9-9     CR2 Format
Fig.10-1    Contents of EDX after RESET
Fig.10-2    Initial Contents of CR0
Fig.10-3    TLB Structure
Fig.10-4    Test Registers
Fig.12-1    Debug Registers
Fig.14-1    Real-Address Mode Address Formation
Fig.15-1    V86 Mode Address Formation
Fig.15-2    Entering and Leaving an 8086 Program
Fig.15-3    PL 0 Stack after Interrupt in V86 Task
Fig.16-1    Stack after Far 16-Bit and 32-Bit Calls
Fig.17-1    80386 Instruction Format
Fig.17-2    ModR/M and SIB Byte Formats
Fig.17-3    Bit Offset for BIT[EAX, 21]
Fig.17-4    Memory Bit Indexing
Fig.A-1 One-Byte Opcode Map I
Fig.A-2 One-Byte Opcode Map II
Fig.A-3 Two-Byte Opcode Map I
Fig.A-4 Two-Byte Opcode Map II
Fig.A-5 Opcodes determined by bits 5,4,3 of modR/M byte:
Fig.B-1  Segment Descriptor Access Bytes
Fig.B-2  Error Code Format (on the stack)
Fig.B-3  Selector Fields
Fig.B-4  Gate Descriptor Format
Fig.B-5  Task State Segment and TSS Registers
Fig.B-6  TSS Descriptor
Fig.B-7  Task Gate Descriptor
Fig.B-8  IDT Selector Error Code
Fig.B-10  Trap/Interrupt Gate Descriptors
Fig.B-11 /n Instruction Byte Format
Fig.B-12 /r Instruction Byte Format
Table B-1. ModRM Values
Table B-3. Hexadecimal Values for the Access Rights Byte