Figures Fig.8
Fig.8-1 Memory-Mapped I/O
Figure 8-1. Memory-Mapped I/O
MEMORY
ADDRESS SPACE I/O DEVICE 1
+---------------+ +-------------------+
| | | INTERNAL REGISTER |
|---------------| - - - - - - - - -|-+---------------+ |
| | | | | |
|---------------| - - - - - - - - -|-+---------------+ |
| | +-------------------+
| |
| |
| |
| | I/O DEVICE 2
| | +-------------------+
| | | INTERNAL REGISTER |
|---------------| - - - - - - - - -|-+---------------+ |
| | | | | |
|---------------| - - - - - - - - -|-+---------------+ |
| | +-------------------+
+---------------+
Fig.8-2 I/O Address Bit Map
Figure 8-2. I/O Address Bit Map
TSS SEGMEMT
31 23 15 7 0
+--------+--------+--------+--------+
LIMIT--->| |
| - - - - - - - - - - - - - - - - - |
. .
. I/O PERMISSION BIT MAP .
. .
| - - - - - - - - - - - - - - - - - |
+---->| |
| |--------+--------+--------+--------|
| . .
| . .
| . .
| |--------+--------+--------+--------|
+-----| I/O MAP BASE |uuuuuuuu uuuuuuuT|64
|--------+--------+--------+--------|
|00000000 00000000| LOT |60
|--------+--------+--------+--------|
|00000000 00000000| GS |5C
|--------+--------+--------+--------|
| |58
. .
. .
. .
| |4
|--------+--------+--------+--------|
|00000000 00000000| TSS BACK LINK |0
+--------+--------+--------+--------+